VHDL语言程序设计-3/8译码器,七段译码器,8/3优先级编码器,D触发器 38译码器vhdl

VHDL时序逻辑设计

1.VHDL设计3-8译码器:

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYdocoder3-8IS

PORT(X: OUT STD_LOGICVECTOR(7 DOWNTO 0);

ENTER:IN STD_LOGIC_VEXTOR(2 DOWNTO 0);

G1,G2a,G2b: IN STD_LOGIC);

ENDENTITYdocoder3-8;

ARCHITECTUREDECODER_ARCHITECTUREIS

BEGIN

PROCESS(ENTER, G1,G2a,G2b)

BEGIN

IF(G1=’1’ ANDG2a+G2b=’0’)THEN

CASEENTERIS

WHEN"000" =>X<= "00000001";

WHEN"001" =>X<= "00000010";

WHEN"010" =>X<= "00000100";

WHEN"011" =>X<= "00001000";

WHEN "100"=> X<= "00010000";

WHEN "101"=> X<= "00100000";

WHEN "110"=> X<= "01000000";

WHEN "111"=> X<= "10000000";

ENDCASE;

ELSEX<= "ZZZZZZZZ";

END IF;

ENDPROCESS;

ENDARCHITECTUREDECODER_ ARCHITECTURE;

2.VHDL设计七段译码器:

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

USEIEEE.STD_LOGIC_ARITH.ALL;

ENTITYSeven-Segment-DecoderIS

PORT(enter:IN STD_logic_vector(3 downto0);

out:out std_logic_vector(6 downto 0));

endENTITYSeven-Segment-Decoder;

architectureDecoder_ architecture ofSeven-Segment-Decoderis

begin

withenter select

out<="1111110" when"0000",

"0110000"when "0001",

"1101101"when "0010",

"1111001"when "0011",

"0110011"when "0100",

"1011011"when "0101",

"1011111"when "0110",

"1110000"when "0111",

"1111111"when "1000",

"1111011"when "1001",

"0000000"when others;

endarchitectureDecoder_ architecture;

3.VHDL设计8/3优先级编码器:

LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYPriority_encoder8/3 IS
PORT(SIGNALy0,y1,y2,y3,y4,y5,y6,y7:INSTD_LOGIC;
SIGNAL OUT:OUTSTD_LOGIC_VECTOR(2 DOWNTO0));
ENDENTITYPriority_encoder 8/3;
ARCHITECTUREEncoder_architectureOFPriority_encoder8/3 IS
BEGIN
PROCESS(y0,y1,y2,y3,y4,y5,y6,y7)
BEGIN
IF (y7='1')THEN
OUT<="111";
ELSIF (y6='0')THEN
OUT<="110";
ELSIF (y5='0')THEN
OUT<="101";
ELSIF (INPUT(3)='0' THEN
OUT<="100";
ELSIF (y4='0')THEN
OUT<="011";
ELSIF (y3='0')THEN
OUT<="010";
ELSIF (y2='0')THEN
OUT<="001";
ELSIF
OUT<="000";
END IF;
ENDPROCESS;
VHDL语言程序设计-3/8译码器,七段译码器,8/3优先级编码器,D触发器 38译码器vhdl
ENDARCHITECTUREEncoder_architecture;

4.VHDL设计由D触发器组成的四位寄存器:

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

ENTITYRegister_4IS

PORT(CLK,CLR:INSTD_LOGIC;

D:INSTD_LOGIC_VECTOR(3 downto0);

Q: OUTSTD_LOGIC_VECTOR(3 downto0));

ENDRegister_4;

ARCHITECTUREBEHAVE_1OFRegister_4IS

SIGNALQ_temp:STD_LOGIC _VECTOR(3 downto0);

BEGIN

PROCESS(clk,CLr)

BEGIN

IF(CLR=’0’)THEN

Q_temp<="0000";

ELSIF(CLK′eventAND clk=′1′)THEN

Q_temp<=D;

END IF;

Q<=Q_temp;

END PROCESS;

ENDARCHITECTUREBEHAVE_1;

5. VHDL设计可逆格雷码计数器:

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

ENTITYGray_CountorIS

PORT(CLK,y:INSTD_LOGIC;

Q: OUTSTD_LOGIC_VECTOR(2 downto 0));

ENDENTITYGray_Countor;

ARCHITECTUREGray_Countor_ArchitectureOFGray_CountorIS

SIGNALQ_temp:STD_LOGIC _VECTOR(2downto0);

BEGIN

PROCESS(CLK)

BEGIN

IF(CLK′eventAND clk=′1′)THEN

IF(y=’1’)THEN

CASEQ_tempIS

WHEN“000”=>Q_temp<=”001”;

WHEN“001”=>Q_temp<=”011”;

WHEN“011”=>Q_temp<=”010”;

WHEN“010”=>Q_temp<=”110”;

WHEN“110”=>Q_temp<=”111”;

WHEN“111”=>Q_temp<=”101”;

WHEN“101”=>Q_temp<=”100”;

WHEN others=>Q_temp<=”000”;

ENDCASE;

END IF;

IF(y=’0’)THEN

CASEQ_tempIS

WHEN“000”=>Q_temp<=”100”;

WHEN“100”=>Q_temp<=”101”;

WHEN“101”=>Q_temp<=”111”;

WHEN“111”=>Q_temp<=”110”;

WHEN“110”=>Q_temp<=”010”;

WHEN“010”=>Q_temp<=”011”;

WHEN“011”=>Q_temp<=”001”;

WHEN others=>Q_temp<=”000”;

END CASE;

END IF;

END IF;

ENDPROCESS;

Q<=Q_temp;

ENDARCHITECTUREGray_Countor_Architecture;

6.VHDL设计有限状态自动机:

LIBRARYIEEE;

USEIEEE.STD_LOGIC_1164.ALL;

ENTITYSEQIS

PORT(CLK,k,Reset: IN STD_LOGIC;

Q: OUT STD_LOGIC _VECTOR(1downto0));

ENDENTITYSEQ;

ARCHITECTURESEQ_ArchitectureOF SEQIS

TYPESEQ_stateIS(S0,S1,S2,S3);

SIGNALCurrent_state,Next_state: SEQ_ state;

BEGIN

reg: PROCESS(CLK,Reset)

BEGIN

IF(Reset=’1’)THEN

Current_state<=S0;

ELSIF(CLK’EVENT ANDCLK=’1’)THEN

Current_state<=Next_state;

END IF;

ENDPROCESS;

com: PROCESS(Current_state,k)

BEGIN

CASECurrent_stateIS

WHENS0=>Q<=”00”;

IF(k=’0’)THEN

Next_state<=S1;

ELSE

Next_state<=S0;

END IF;

WHENS1=>Q<=”01”

IF(k=’0’)THEN

Next_state<=S1;

ELSE

Next_state<=s2;

END IF;

WHENS2=>Q<=”10”;

IF(k=’0’)THEN

Next_state<=S3;

ELSE

Next_state<=S2;

END IF;

WHENS3=>Q<=”11”;

IF(k=’0’)THEN

Next_state<=S3;

ELSE

Next_state<=S0;

END IF;

WHEN others=>Next_state<=S0;

END CASE;

END PROCESS;

ENDARCHITECTURESEQ_Architecture;

  

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